老大們幫忙看看POST結(jié)果，我懷疑內(nèi)存有問(wèn)題

maigan02

結(jié)果如下：

@(#) Sun Ultra 5/10 UPA/PCI 3.29 Version 0 created 2000/12/20 18:45
Probing keyboard Done
%o0 = 0000.0000.0000.4001

Executing Power On SelfTest

@(#) Sun Ultra 5/10 (Darwin) POST 3.1.0 (Build No. 626) 13:56 on 06/27/00

CPU: UltraSPARC-LC (Clock Frequency: 440MHz, Ecache Size: 2048KB)

Init POST BSS
        Init System BSS
NVRAM
        NVRAM Battery Detect Test
        NVRAM Scratch Addr Test
        NVRAM Scratch Data Test
DMMU TLB Tags
        DMMU TLB Tag Access Test
DMMU TLB RAM
        DMMU TLB RAM Access Test
Probe Ecache
        Probe Ecache
Ecache Tests
        Ecache RAM Addr Test
        Ecache Tag Addr Test
        Ecache RAM Test
        Ecache Tag Test
All CPU Basic Tests
        V9 Instruction Test
        CPU Tick and Tick Compare Reg Test
        CPU Soft Trap Test
        CPU Softint Reg and Int Test
All Basic MMU Tests
        DMMU Primary Context Reg Test
        DMMU Secondary Context Reg Test
        DMMU TSB Reg Test
        DMMU Tag Access Reg Test
        DMMU VA Watchpoint Reg Test
        DMMU PA Watchpoint Reg Test
        IMMU TSB Reg Test
        IMMU Tag Access Reg Test
All Basic Cache Tests
        Dcache RAM Test
        Dcache Tag Test
        Icache RAM Test
        Icache Tag Test
        Icache Next Test
        Icache Predecode Test
Memory Probe
        Probe Memory
                bank 0:   0MB
                INFO:    512MB Bank 2
Sabre MCU Control & Status Regs Init and Tests
        Init Sabre MCU Control & Status Regs
                Initializing SC registers in SabreIO
Memory Init
        Ecache Access Test
        Malloc Post Memory
        Memory Addr with Ecache
        Load Post In Memory
        Run POST from MEM
        ..........
loaded POST in memory
        Map PROM/STACK/NVRAM in DMMU
        Update Master Stack/Frame Pointers
All FPU Basic Tests
        FPU Regs Test
        FPU Move Regs Test
        FPU State Reg Test
        FPU Functional Test
        FPU Trap Test
UPA Data Bus Line Test
Memory Tests
        Init Memory
                INFO:      0MB at bank 0 stack 0
                INFO:      0MB at bank 0 stack 1
                INFO:    256MB at bank 2 stack 0 (2 dimms per bank)
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                INFO:    256MB at bank 2 stack 1 (2 dimms per bank)
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        Memory Addr with Ecache Test
                INFO:      0MB at bank 0 stack 0
                INFO:      0MB at bank 0 stack 1
                INFO:    256MB at bank 2 stack 0 (2 dimms per bank)
                INFO:    256MB at bank 2 stack 1 (2 dimms per bank)
        ECC Memory Addr Test
                INFO:      0MB at bank 0 stack 0
                INFO:      0MB at bank 0 stack 1
                INFO:    256MB at bank 2 stack 0 (2 dimms per bank)
                INFO:    256MB at bank 2 stack 1 (2 dimms per bank)
        Block Memory Addr Test
                INFO:      0MB at bank 0 stack 0
                INFO:      0MB at bank 0 stack 1
                INFO:    256MB at bank 2 stack 0 (2 dimms per bank)
                INFO:    256MB at bank 2 stack 1 (2 dimms per bank)
        Block Memory Test
                INFO:      0MB at bank 0 stack 0
                INFO:      0MB at bank 0 stack 1
                INFO:    256MB at bank 2 stack 0 (2 dimms per bank)
Write 0x33333333.33333333 ......................................................
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Read ...........................................................................
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Write 0x55555555.55555555 ......................................................
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Read ...........................................................................
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Write 0xcccccccc.cccccccc ......................................................
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Read ...........................................................................
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Write 0xaaaaaaaa.aaaaaaaa ......................................................
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Read ...........................................................................
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                INFO:    256MB at bank 2 stack 1 (2 dimms per bank)
Write 0x33333333.33333333 ......................................................
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Read ...........................................................................
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Write 0x55555555.55555555 ......................................................
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Read ...........................................................................
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Write 0xcccccccc.cccccccc ......................................................
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Read ...........................................................................
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Write 0xaaaaaaaa.aaaaaaaa ......................................................
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Read ...........................................................................
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        ECC Blk Memory Test
                INFO:      0MB at bank 0 stack 0
                INFO:      0MB at bank 0 stack 1
                INFO:    256MB at bank 2 stack 0 (2 dimms per bank)
Write 0xa5a5a5a5.a5a5a5a5 ......................................................
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Read ...........................................................................
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Write 0x96969696.96969696 ......................................................
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Read ...........................................................................
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Write 0xbbbbbbbb.bbbbbbbb ......................................................
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Read ...........................................................................
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Write 0xdddddddd.dddddddd ......................................................
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Read ...........................................................................
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                INFO:    256MB at bank 2 stack 1 (2 dimms per bank)
Write 0xa5a5a5a5.a5a5a5a5 ......................................................
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Read ...........................................................................
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Write 0x96969696.96969696 ......................................................
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Read ...........................................................................
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Write 0xbbbbbbbb.bbbbbbbb ......................................................
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Read ...........................................................................
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Write 0xdddddddd.dddddddd ......................................................
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Read ...........................................................................
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All Basic Sabre MMU Tests
        Init Sabre
        PIO Decoder and BCT Test
        PCI Byte Enable Test
        Interrupt Map (short) Reg Test
        Interrupt Set/Clr Reg Test
        Sabre IOMMU Regs Test
        Sabre IOMMU RAM Address Test
        Sabre IOMMU CAM Address Test
        IOMMU TLB Compare Test
        IOMMU TLB Flush Test
        PBMA PCI Config Space Regs Test
        PBMA Control/Status Reg Test
        PBMA Diag Reg Test
        Sabre IO Regs Test
All Advanced CPU Tests
        DMMU Hit/Miss Test
        IMMU Hit/Miss Test
        DMMU Little Endian Test
        IU ASI Access Test
        FPU ASI Access Test
        Ecache Thrash Test
All CPU Error Reporting Tests
        CPU Data Access Trap Test
        CPU Addr Align Trap Test
        DMMU Access Priv Page Test
        DMMU Write Protected Page Test
All Advanced Sabre IOMMU Tests
        Init Sabre
        Consist DMA Rd, IOMMU miss Ebus Test
        Consist DMA Rd, IOMMU hit Ebus Test
        Consist DMA Wr, IOMMU miss Ebus Test
        Consist DMA Wr, IOMMU hit Ebus Test
        Pass-Thru DMA Rd, Ebus device Test
        Pass-Thru DMA Wr, Ebus device Test
        Consist DMA Rd, IOMMU LRU Lock Ebus Test
        Consist DMA Wr, IOMMU LRU Locked Ebus Test
All Basic Cheerio Tests
        Cheerio Ebus PCI Config Space Test
        Cheerio Ethernet PCI Config Space Test
        Cheerio Init
All Sabre IOMMU Error Reporting Tests
        Init Sabre
        PIO Read, Master Abort Test
        PIO Read, Target Abort Test


Status of this POST run:        PASS
manfacturing mode=OFF
Time Stamp [hour] 01:33:11  [month/date year] 06/05 2005




Power On Selftest Completed
    Status  = 0000.0000.0000.0000 ffff.ffff.f00Software Power ON

@(#) Sun Ultra 5/10 UPA/PCI 3.29 Version 0 created 2000/12/20 18:45
Clearing E$ Tags  Done
Clearing I/D TLBs Done
Probing Memory Done
MEM BASE = 0000.0000.3000.0000
MEM SIZE = 0000.0000.1000.0000
11-Column Mode Enabled
MMUs ON
Copy Done
PC = 0000.01ff.f000.201c
PC = 0000.0000.0000.2060
Decompressing into Memory Done
Size = 0000.0000.0006.e770
ttya initialized
Reset Control: BXIR:0 BPOR:0 SXIR:0 SPOR:1 POR:0
UltraSPARC-IIi 2-2 module
Probing Memory Bank #0   0 +   0 :   0 Megabytes
Probing Memory Bank #2 256 + 256 : 512 Megabytes
Probing UPA Slot at 1e,0
到了這里就死機(jī)了。機(jī)器為U10，用串口連的，不能中斷進(jìn)入OK。

jobandmiss

內(nèi)存沒(méi)事啊
Probing UPA Slot at 1e,0
應(yīng)是板子

大飛象

懷疑顯卡

sunyeait

請(qǐng)把你主機(jī)的鍵盤和鼠標(biāo)拔掉，再加電做POSt,你可以中斷進(jìn)入OK狀態(tài)；  
post信息已經(jīng)顯示在你終端上，說(shuō)明你聯(lián)結(jié)方法是好的；只是在經(jīng)過(guò)自檢之后，系統(tǒng)輸出轉(zhuǎn)移到screen和keyboard上去了；
這種情況，已經(jīng)把我害慘了：（

maigan02

原帖由 "sunyeait" 發(fā)表：
請(qǐng)把你主機(jī)的鍵盤和鼠標(biāo)拔掉，再加電做POSt,你可以中斷進(jìn)入OK狀態(tài)；  
post信息已經(jīng)顯示在你終端上，說(shuō)明你聯(lián)結(jié)方法是好的；只是在經(jīng)過(guò)自檢之后，系統(tǒng)輸出轉(zhuǎn)移到screen和keyboard上去了；
這種情況，已經(jīng)把我害慘?.........

本來(lái)就沒(méi)有接鼠標(biāo)和鍵盤。   

metor78

同意顯卡故障

jobandmiss

顯示卡也是集成在板子上的
在檢測(cè)UPA總線其中的一個(gè)接口時(shí)過(guò)不去
感覺(jué)得換板子

bingfeng76

U10機(jī)器出問(wèn)題最多的是CPU。