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v480 啟動不了了，從串口看，發(fā)現一直再重復自檢，下面是自檢信息，請大家?guī)臀铱匆幌率悄莾撼隽藛栴}，謝謝！<*>;
Hardware Power On
@(#)OBP 4.10.8 2003/07/25 08:44 Sun Fire 480R
Front Panel Keyswitch is in Diagnostic position.
Online: CPU0 CPU1 CPU2 CPU3*
Validating JTAG integrity...Done
Disabling DAR error circuitry...Done
Clearing DCS error circuitry state...Done
Initializing DTL circuitry state...Done
Initializing CDX via JTAG...Done
Enabling DAR error circuitry...Done
Probing Centerplane....part# 501-6780-01 serial# 005673
Safari min 100MHz, cumulative 100MHz; max 150MHz, cumulative 150MHz
'STICK' clock 10MHz; BootBus timing 014f.99fd.a7e6.3f29
Probing I/O Riser......part# 501-5820-04 serial# 058119
Probing System RSC.....part# 501-5856-06 serial# 236107
Probing PwrDistBoard...part# 375-3006-05 serial# M63721
Probing PowerSupply0...part# 300-1480-05 serial# N32098
Probing PowerSupply1...part# 300-1480-05 serial# N32094
Probing FCAL BPlane0...part# 501-5822-04 serial# 059658
Probing GPTwo Slot A...part# 501-6164-02 serial# 026662
Safari min 100MHz, cumulative 100MHz; max 150MHz, cumulative 150MHz
CPU rated speed 1200MHz; ECache 8MB 3.3ns
Probing GPTwo Slot B...part# 501-6164-02 serial# 026626
Safari min 100MHz, cumulative 100MHz; max 150MHz, cumulative 150MHz
CPU rated speed 1200MHz; ECache 8MB 3.3ns
Desired Safari Bus speed 150MHz, selecting 150MHz
Configuring CPUs..........
... CPU0 Rated Speed 1200MHz, Safari 150MHz, want 8:1, got 8:1 ==>; CPU 1200MHz
Ecache 8MB 3.3ns mode=5-4-4 2-way ECCR: 0000.0000.0343.4c00
... CPU1 Rated Speed 1200MHz, Safari 150MHz, want 8:1, got 8:1 ==>; CPU 1200MHz
Ecache 8MB 3.3ns mode=5-4-4 2-way ECCR: 0000.0000.0343.4c00
... CPU2 Rated Speed 1200MHz, Safari 150MHz, want 8:1, got 8:1 ==>; CPU 1200MHz
Ecache 8MB 3.3ns mode=5-4-4 2-way ECCR: 0000.0000.0343.4c00
... CPU3 Rated Speed 1200MHz, Safari 150MHz, want 8:1, got 8:1 ==>; CPU 1200MHz
Ecache 8MB 3.3ns mode=5-4-4 2-way ECCR: 0000.0000.0343.4c00 Done
Setting system speed (and resetting)...
<*>;
Set Speed Reset
@(#)OBP 4.10.8 2003/07/25 08:44 Sun Fire 480R
Front Panel Keyswitch is in Diagnostic position.
Online: CPU0 Ultra-III+ (v11.1) 8:1 1200MHz 8MB 4:1 ECache
Online: CPU1 Ultra-III+ (v11.1) 8:1 1200MHz 8MB 4:1 ECache
Online: CPU2 Ultra-III+ (v11.1) 8:1 1200MHz 8MB 4:1 ECache
Online: *CPU3 Ultra-III+ (v11.1) 8:1 1200MHz 8MB 4:1 ECache
Executing Power On SelfTest w/%o0 = 0000.0000.0001.2042
0>;@(#) Cherrystone POST 4.10.8 2003/07/24 18:07
/export/common-source/firmware_re/post/post-build-4.10.8/Camelot/cstone/integrated (firmware_re)
0>;Jump from OBP-> OST.
0>;CPUs present in system: 0 1 2 3
0>;Keyswitch in DIAGNOSTIC POSITION.
0>;Diag level set to MIN.
0>;MFG scrpt mode set NORM
0>;I/O port set to serial TTYA.
0>;
0>;Start selftest...
0>;Init CPU
0>; Cheetah_plus Version 11.1
0>;DMMU Registers Access
0>;DMMU TLB DATA RAM Access
0>;DMMU TLB TAGS Access
0>;IMMU Registers Access
0>;IMMU TLB DATA RAM Access
0>;IMMU TLB TAGS Access
0>robe Ecache
0>; Size = 00000000.00800000...
0>;Ecache Data Bitwalk
0>;Ecache Address Bitwalk
0>;Scrub and Setup Ecache
0>;Setup and Enable DMMU
0>;Setup DMMU Miss Handler
0>;Test and Init Temp Mailbox
1>;Init CPU
2>;Init CPU
3>;Init CPU
1>; Cheetah_plus Version 11.1
2>; Cheetah_plus Version 11.1
3>; Cheetah_plus Version 11.1
1>;DMMU Registers Access
2>;DMMU Registers Access
3>;DMMU Registers Access
1>;DMMU TLB DATA RAM Access
2>;DMMU TLB DATA RAM Access
3>;DMMU TLB DATA RAM Access
1>;DMMU TLB TAGS Access
2>;DMMU TLB TAGS Access
3>;DMMU TLB TAGS Access
1>;IMMU Registers Access
2>;IMMU Registers Access
3>;IMMU Registers Access
1>;IMMU TLB DATA RAM Access
2>;IMMU TLB DATA RAM Access
3>;IMMU TLB DATA RAM Access
1>;IMMU TLB TAGS Access
2>;IMMU TLB TAGS Access
3>;IMMU TLB TAGS Access
1>robe Ecache
1>; Size = 00000000.00800000...
2>robe Ecache
2>; Size = 00000000.00800000...
3>robe Ecache
3>; Size = 00000000.00800000...
1>;Ecache Data Bitwalk
2>;Ecache Data Bitwalk
3>;Ecache Data Bitwalk
1>;Ecache Address Bitwalk
2>;Ecache Address Bitwalk
3>;Ecache Address Bitwalk
1>;Scrub and Setup Ecache
2>;Scrub and Setup Ecache
3>;Scrub and Setup Ecache
1>;Setup and Enable DMMU
2>;Setup and Enable DMMU
3>;Setup and Enable DMMU
1>;Setup DMMU Miss Handler
2>;Setup DMMU Miss Handler
3>;Setup DMMU Miss Handler
1>;Test and Init Temp Mailbox
2>;Test and Init Temp Mailbox
3>;Test and Init Temp Mailbox
0>;Initializing Scan Database
0>;Mask DAR errors off
0>;Init CDX DTL
0>;Init DAR DTL
0>;Enable Partial DAR error
0>;Init DCS DTL
0>;Init I2C
0>;Unquiesce Safari
0>;Margin all voltages to nominal
0>;Scan ring integrity
0>;Set Trip Temp CPU 0 to 110C
0>;Set Trip Temp CPU 1 to 110C
0>;Set Trip Temp CPU 2 to 110C
0>;Set Trip Temp CPU 3 to 110C
0>;FRI AUG 20 6:55:41 GMT 4
0>;Safari quick check
0>; to IO-bridge_0
0>; to IO-bridge_1
0>;Safari full check
0>; to IO-bridge_0
0>; to IO-bridge_1
0>;Disable Cheetah 0 error checking
0>;Disable Cheetah 1 error checking
0>;Disable Cheetah 2 error checking
0>;Disable Cheetah 3 error checking
0>robe and Setup Memory
0>;INFO: 1024MB Bank 0
0>;INFO: 1024MB Bank 1
0>;INFO: 1024MB Bank 2
0>;INFO: 1024MB Bank 3
0>;
0>;Data Bitwalk on Master
0>; Test Bank 0.
0>; Test Bank 1.
0>; Test Bank 2.
0>; Test Bank 3.
0>;Address Bitwalk on Master
0>;INFO: Addr walk mem test on CPU 0 Bank 0: 00000000.00000000 to 00000000.40000000.
0>;INFO: Addr walk mem test on CPU 0 Bank 1: 00000001.00000000 to 00000001.40000000.
0>;INFO: Addr walk mem test on CPU 0 Bank 2: 00000002.00000000 to 00000002.40000000.
0>;INFO: Addr walk mem test on CPU 0 Bank 3: 00000003.00000000 to 00000003.40000000.
0>;Set Mailbox
0>;Setup Final DMMU Entries
0>ost Image Region Scrub
0>;Run POST from Memory
0>;Verifying checksum on copied image.
0>;The Memory's CHECKSUM value is 9d6c.
0>;The Memory's Content Size value is 9067a.
0>;Success... Checksum on Memory Validated.
0>;Safari quick check
0>; to IO-bridge_0
0>; to IO-bridge_1
0>;Safari full check
0>; to IO-bridge_0
0>; to IO-bridge_1
1>;Safari quick check
1>; to IO-bridge_0
1>; to IO-bridge_1
1>;Safari full check
1>; to IO-bridge_0
1>; to IO-bridge_1
2>;Safari quick check
2>; to IO-bridge_0
0>;BBC1 Reset!
0>;
0>;Start selftest...
0>;Init CPU
0>; Cheetah_plus Version 11.1
0>;DMMU Registers Access
0>;DMMU TLB DATA RAM Access
0>;DMMU TLB TAGS Access
0>;IMMU Registers Access
0>;IMMU TLB DATA RAM Access
0>;IMMU TLB TAGS Access
0>robe Ecache
0>; Size = 00000000.00800000...
0>;Ecache Data Bitwalk
0>;Ecache Address Bitwalk
0>;Scrub and Setup Ecache
0>;Setup and Enable DMMU
0>;Setup DMMU Miss Handler
0>;Test and Init Temp Mailbox
1>;Init CPU
1>; Cheetah_plus Version 11.1
2>;Init CPU
3>;Init CPU
1>;DMMU Registers Access
2>; Cheetah_plus Version 11.1
3>; Cheetah_plus Version 11.1
2>;DMMU Registers Access
3>;DMMU Registers Access
1>;DMMU TLB DATA RAM Access
2>;DMMU TLB DATA RAM Access
3>;DMMU TLB DATA RAM Access
1>;DMMU TLB TAGS Access
2>;DMMU TLB TAGS Access
3>;DMMU TLB TAGS Access
1>;IMMU Registers Access
2>;IMMU Registers Access
3>;IMMU Registers Access
1>;IMMU TLB DATA RAM Access
2>;IMMU TLB DATA RAM Access
3>;IMMU TLB DATA RAM Access
1>;IMMU TLB TAGS Access
2>;IMMU TLB TAGS Access
3>;IMMU TLB TAGS Access
1>robe Ecache
1>; Size = 00000000.00800000...
2>robe Ecache
2>; Size = 00000000.00800000...
3>;Probe Ecache
3>; Size = 00000000.00800000...
1>;Ecache Data Bitwalk
2>;Ecache Data Bitwalk
3>;Ecache Data Bitwalk
1>;Ecache Address Bitwalk
2>;Ecache Address Bitwalk
3>;Ecache Address Bitwalk
1>;Scrub and Setup Ecache
2>;Scrub and Setup Ecache
3>;Scrub and Setup Ecache
1>;Setup and Enable DMMU
2>;Setup and Enable DMMU
3>;Setup and Enable DMMU
1>;Setup DMMU Miss Handler
2>;Setup DMMU Miss Handler
3>;Setup DMMU Miss Handler
1>;Test and Init Temp Mailbox
2>;Test and Init Temp Mailbox
3>;Test and Init Temp Mailbox
0>;Initializing Scan Database
0>;Mask DAR errors off
0>;Init CDX DTL
0>;Init DAR DTL
0>;Enable Partial DAR error
0>;Init DCS DTL
0>;Init I2C
0>;Unquiesce Safari
0>;Margin all voltages to nominal
0>;Scan ring integrity
0>;Set Trip Temp CPU 0 to 110C
0>;Set Trip Temp CPU 1 to 110C
0>;Set Trip Temp CPU 2 to 110C
0>;Set Trip Temp CPU 3 to 110C
0>;FRI AUG 20 6:56:51 GMT 4
0>;Safari quick check
0>; to IO-bridge_0
0>; to IO-bridge_1
0>;Safari full check
0>; to IO-bridge_0
0>; to IO-bridge_1
0>;Disable Cheetah 0 error checking
0>;Disable Cheetah 1 error checking
0>;Disable Cheetah 2 error checking
0>;Disable Cheetah 3 error checking
0>;Probe and Setup Memory
0>;INFO: 1024MB Bank 0
0>;INFO: 1024MB Bank 1
0>;INFO: 1024MB Bank 2
0>;INFO: 1024MB Bank 3
0>;
0>;Data Bitwalk on Master
0>; Test Bank 0.
0>; Test Bank 1.
0>; Test Bank 2.
0>; Test Bank 3.
0>;Address Bitwalk on Master
0>;INFO: Addr walk mem test on CPU 0 Bank 0: 00000000.00000000 to 00000000.40000000.
0>;INFO: Addr walk mem test on CPU 0 Bank 1: 00000001.00000000 to 00000001.40000000.
0>;INFO: Addr walk mem test on CPU 0 Bank 2: 00000002.00000000 to 00000002.40000000.
0>;INFO: Addr walk mem test on CPU 0 Bank 3: 00000003.00000000 to 00000003.40000000.
0>;Set Mailbox
0>;Setup Final DMMU Entries
0>;Post Image Region Scrub
0>;Run POST from Memory
0>;Verifying checksum on copied image.
0>;The Memory's CHECKSUM value is 9d6c.
0>;The Memory's Content Size value is 9067a.
0>;Success... Checksum on Memory Validated.
0>;Safari quick check
0>; to IO-bridge_0
0>; to IO-bridge_1
0>;Safari full check
0>; to IO-bridge_0
0>; to IO-bridge_1
1>;Safari quick check
1>; to IO-bridge_0
1>; to IO-bridge_1
1>;Safari full check
1>; to IO-bridge_0
1>; to IO-bridge_1
2>;Safari quick check
2>; to IO-bridge_0
0>;BBC1 Reset!
0>;
0>;Start selftest...
0>;Init CPU
0>; Cheetah_plus Version 11.1
0>;DMMU Registers Access
0>;DMMU TLB DATA RAM Access
0>;DMMU TLB TAGS Access
0>;IMMU Registers Access
0>;IMMU TLB DATA RAM Access
0>;IMMU TLB TAGS Access
0>;Probe Ecache
0>; Size = 00000000.00800000...
0>;Ecache Data Bitwalk
0>;Ecache Address Bitwalk
0>;Scrub and Setup Ecache
0>;Setup and Enable DMMU
0>;Setup DMMU Miss Handler
0>;Test and Init Temp Mailbox
1>;Init CPU
1>; Cheetah_plus Version 11.1
2>;Init CPU
3>;Init CPU
1>;DMMU Registers Access
2>; Cheetah_plus Version 11.1
3>; Cheetah_plus Version 11.1
2>;DMMU Registers Access
3>;DMMU Registers Access
1>;DMMU TLB DATA RAM Access
2>;DMMU TLB DATA RAM Access
3>;DMMU TLB DATA RAM Access
1>;DMMU TLB TAGS Access
2>;DMMU TLB TAGS Access
3>;DMMU TLB TAGS Access
1>;IMMU Registers Access
2>;IMMU Registers Access
3>;IMMU Registers Access
1>;IMMU TLB DATA RAM Access
2>;IMMU TLB DATA RAM Access
3>;IMMU TLB DATA RAM Access
1>;IMMU TLB TAGS Access
2>;IMMU TLB TAGS Access
3>;IMMU TLB TAGS Access
1>;Probe Ecache
1>; Size = 00000000.00800000...
2>;Probe Ecache
2>; Size = 00000000.00800000...
3>;Probe Ecache
3>; Size = 00000000.00800000...
1>;Ecache Data Bitwalk
2>;Ecache Data Bitwalk
3>;Ecache Data Bitwalk
1>;Ecache Address Bitwalk
2>;Ecache Address Bitwalk
3>;Ecache Address Bitwalk |
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免費注冊
發(fā)表于 2004-08-20 15:00
