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Hardware Reset...\r\n\r\n\r\n@(#) SYSTEM CONTROLLER(SC) POST 43 2005/02/22 15:29\r\nPSR = 0x044010e5\r\nPCR = 0x04004000\r\n\r\n Memory size = 32MB\r\n\r\n SelfTest running at DiagLevel:0x20\r\n \r\nSC Boot PROM Test \r\n BootPROM CheckSum Test \r\nIU Test \r\n IU instruction set Test \r\n Little endian access Test \r\nFPU Test \r\n FPU instruction set Test \r\nSparcReferenceMMU Test \r\n SRMMU TLB RAM Test \r\n SRMMU TLB Read miss Test \r\n SRMMU page probe Test \r\n SRMMU segment probe Test \r\n SRMMU region probe Test \r\n SRMMU context probe Test \r\nIIep Internal Cache Test \r\n DCACHE RAM access Test \r\n DCACHE TAG access Test \r\n DCACHE Read miss Test \r\n DCACHE Read hit Test \r\n DCACHE Write miss Test \r\n DCACHE Write hit Test \r\n ICACHE RAM access Test \r\n ICACHE TAG access Test \r\n ICACHE miss Test \r\n ICACHE hit Test \r\n ICACHE TAG flush Test \r\nPCIC Test \r\n PCIC Probe Test \r\n PCIC Config Register Access Test \r\n PCI Master Abort Test \r\n PCIC Init Test \r\nMemory Test \r\n Memory Address Test\r\n MemBankAddrTest: start address = 0x00010000 \r\nRIO Ebus Test \r\n Rio Ebus Probe Test \r\nRIO Ethernet Test \r\n Rio Enet Probe Test \r\n Rio Ethernet Int Loopbacks Test \r\nDUART(16552) InterSC Test \r\n Loopback Test\r\n COM3 port\r\n COM4 port \r\n Interrupt Test\r\n COM3 port Intr #2\r\n\r\n COM4 port Intr #2\r\n \r\nSystem Clock Test \r\n System Clock verify Test\r\n Board0 Clock is selected\r\n 75MHZ Fixed Crystal is the selected Clock Source\r\n CLK(Self) :0x0000ffff CLK(Other) : 0x0000ffff\r\n REF : 0x00002204\r\n CLOCK(SELF) FREQ : 75.0 MHZ\r\n CLOCK(OTHER) FREQ : 75.25 MHZ \r\nSBBC PCI Controller Test \r\n SBBC PCI Config Space probe Test \r\n SBBC Internal Reg Access Test \r\n SBBC Interrupts Test\r\n Port1 interrupt generation Tests INTR #14\r\n\r\n Port0 interrupt generation Tests INTR #14\r\n \r\nSBBC Device0 Test \r\n PS Fail Reg(SBBC Dev0) Test \r\nSBBC Device1 Test \r\n SRAM (SBBC Dev1) Test\r\n Memory Address Test (Non-destructive) \r\nSBBC Device2 Test \r\n BId&MFG Reg (SBBC Dev2) Test \r\nSBBC Device3 Test \r\n FRU Prsnt Reg (SBBC Dev3) Test \r\nSBBC Device5 Test \r\n EPLD (SBBC Dev5) Test \r\nTOD(M48T59) Test \r\n TOD Init Test \r\n TOD Functional Test \r\n TOD NVRAM(Non-Destructive) Test \r\n TOD Interrupts Test \r\nI2C Register Access Test \r\n Enable Mux Register Test \r\n Channel Mux Register Test \r\n Add Command Register Test \r\n Data Register Test \r\nLocal I2C AT24C64 Test \r\n EEPROM Device Test\r\n performing eeprom sequential read\r\n \r\nLocal I2C PCF8591 Test \r\n VOLT_AD Device Test\r\n channel[00000001] Voltage(0x00000099) :1.49\r\n channel[00000002] Voltage(0x0000009C) :3.35\r\n channel[00000003] Voltage(0x00000099) :4.98\r\n channel[00000004] Voltage(0x00000000) :0.0 \r\nLocal I2C LM75 Test \r\n TEMP0(IIep) Device Test\r\n Temperature : 48.0 Degree(C)\r\n \r\nLocal I2C LM75 Test \r\n TEMP1(Rio) Device Test\r\n Temperature : 42.0 Degree(C)\r\n \r\nLocal I2C LM75 Test \r\n TEMP2(CBH) Device Test\r\n Temperature : 51.0 Degree(C)\r\n \r\nLocal I2C PCF8574 Test \r\n Sc CSR Device Test \r\nConsole Bus Hub Test \r\n CBH Register Access Test\r\nPOST Complete.\r\nERI Device Present\r\nGetting MAC address for SSC0\r\nbusyWait() timeout waiting for RRDY, status=0x6027c008\r\nbusyWait() timeout waiting for RRDY, status=0x6027c008\r\nbusyWait() timeout waiting for RRDY, status=0x6027c008\r\nbusyWait() timeout waiting for WRDY, status=0x60278008\r\nCannot read ID board; using MAC address from TODNVRAM\r\nMAC address is 0:3:ba:9:e0:36\r\nHostname: gb132\r\nAddress: 172.16.10.71\r\nNetmask: 255.255.0.0\r\nAttached TCP/IP interface to eri unit 0\r\nAttaching interface lo0...done\r\nGateway: 172.16.10.254\r\nTimeout waiting for network driver (flags=0x8062)\r\n\r\n\r\n Copyright 2005 Sun Microsystems, Inc. All rights reserved.\r\n Use is subject to license terms.\r\n\r\nSun Fire System Firmware\r\nRTOS version: 43\r\nScApp version: 5.19.0 Build_01.0\r\nSC POST diag level: min\r\nbusyWait() timeout waiting for RRDY, status=0x6027c008\r\n busyWait() timeout waiting for RRDY, status=0x6027c008\r\n busyWait() timeout waiting for RRDY, status=0x6027c008\r\n busyWait() timeout waiting for WRDY, status=0x60278008\r\n\r\nThe date is Friday, May 12, 2006, 9:10:23 PM CST.\r\n\r\nMay 12 21:10:24 gb132 Platform.SC: Boot: ScApp 5.19.0, RTOS 43\r\nMay 12 21:10:27 gb132 Platform.SC: SBBC Reset Reason(s): Power On Reset , SC Reset Button\r\nMay 12 21:10:27 gb132 Platform.SC: Initializing the SC SRAM\r\nMay 12 21:10:30 gb132 Platform.SC: ERROR: Boot Failure, ID0 not installed\r\nMay 12 21:10:30 gb132 Platform.SC: ERROR: Boot Failure, ID0 not installed\r\nERROR: PSU type not recognized, use A166\r\nMay 12 21:10:31 gb132 Platform.SC: SCC is inaccessible - please insert valid SCC |
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免費注冊
發(fā)表于 2006-05-13 09:46
