【學(xué)習(xí)筆記】IAR中cortex-m4啟動(dòng)流程分析（2）

houxn22

    上次寫(xiě)了飛思卡爾官方給出的demo程序的啟動(dòng)流程的前面部分：

    在存儲(chǔ)器最前面放置好向量表-->把通用寄存器清零-->開(kāi)中斷-->跳轉(zhuǎn)到start函數(shù)繼續(xù)執(zhí)行初始化。在start函數(shù)中，順次執(zhí)行三個(gè)函數(shù)：禁用看門(mén)狗-->初始化C語(yǔ)言環(huán)境（向量表重定向、拷貝數(shù)據(jù)段到RAM、清零bss段等）-->系統(tǒng)外設(shè)初始化。

③系統(tǒng)外設(shè)初始化函數(shù) sysinit()

1. #include "common.h"
   
2. #include "sysinit.h"
   
3. #include "uart.h"
   
4. 
   
5. /********************************************************************/
   
6. 
   
7. /* Actual system clock frequency */
   
8. int core_clk_khz;
   
9. int core_clk_mhz;
   
10. int periph_clk_khz;
    
11. 
    
12. /********************************************************************/
    
13. void sysinit (void)
    
14. {
    
15.         /*
    
16.          * Enable all of the port clocks. These have to be enabled to configure
    
17.          * pin muxing options, so most code will need all of these on anyway.
    
18.          */
    
19.         SIM_SCGC5 |= (SIM_SCGC5_PORTA_MASK
    
20.                       | SIM_SCGC5_PORTB_MASK
    
21.                       | SIM_SCGC5_PORTC_MASK
    
22.                       | SIM_SCGC5_PORTD_MASK
    
23.                       | SIM_SCGC5_PORTE_MASK );
    
24. 
    
25.      /* Ramp up the system clock */
    
26.     core_clk_mhz = pll_init(CORE_CLK_MHZ, REF_CLK);
    
27. 
    
28.     /*
    
29.          * Use the value obtained from the pll_init function to define variables
    
30.      * for the core clock in kHz and also the peripheral clock. These
    
31.      * variables can be used by other functions that need awareness of the
    
32.      * system frequency.
    
33.      */
    
34.     core_clk_khz = core_clk_mhz * 1000;
    
35.       periph_clk_khz = core_clk_khz / (((SIM_CLKDIV1 & SIM_CLKDIV1_OUTDIV2_MASK) >> 24)+ 1);
    
36. 
    
37.       /* For debugging purposes, enable the trace clock and/or FB_CLK so that
    
38.        * we'll be able to monitor clocks and know the PLL is at the frequency
    
39.        * that we expect.
    
40.        */
    
41.     trace_clk_init();
    
42.       fb_clk_init();
    
43. 
    
44.       /* Enable the pins for the selected UART */
    
45.          if (TERM_PORT == UART0_BASE_PTR)
    
46.          {
    
47.             /* Enable the UART0_TXD function on PTD6 */
    
48.             PORTD_PCR6 = PORT_PCR_MUX(0x3); // UART is alt3 function for this pin
    
49. 
    
50.             /* Enable the UART0_RXD function on PTD7 */
    
51.             PORTD_PCR7 = PORT_PCR_MUX(0x3); // UART is alt3 function for this pin
    
52.          }
    
53. 
    
54.          if (TERM_PORT == UART1_BASE_PTR)
    
55.        {
    
56.                  /* Enable the UART1_TXD function on PTC4 */
    
57.           PORTC_PCR4 = PORT_PCR_MUX(0x3); // UART is alt3 function for this pin
    
58. 
    
59.           /* Enable the UART1_RXD function on PTC3 */
    
60.           PORTC_PCR3 = PORT_PCR_MUX(0x3); // UART is alt3 function for this pin
    
61.       }
    
62. 
    
63.       if (TERM_PORT == UART2_BASE_PTR)
    
64.       {
    
65.                  /* Enable the UART2_TXD function on PTD3 */
    
66.           PORTD_PCR3 = PORT_PCR_MUX(0x3); // UART is alt3 function for this pin
    
67. 
    
68.           /* Enable the UART2_RXD function on PTD2 */
    
69.           PORTD_PCR2 = PORT_PCR_MUX(0x3); // UART is alt3 function for this pin
    
70.       }
    
71. 
    
72.       if (TERM_PORT == UART3_BASE_PTR)
    
73.       {
    
74.                  /* Enable the UART3_TXD function on PTC17 */
    
75.           PORTC_PCR17 = PORT_PCR_MUX(0x3); // UART is alt3 function for this pin
    
76. 
    
77.           /* Enable the UART3_RXD function on PTC16 */
    
78.           PORTC_PCR16 = PORT_PCR_MUX(0x3); // UART is alt3 function for this pin
    
79.       }
    
80.       if (TERM_PORT == UART4_BASE_PTR)
    
81.       {
    
82.                  /* Enable the UART3_TXD function on PTC17 */
    
83.           PORTE_PCR24 = PORT_PCR_MUX(0x3); // UART is alt3 function for this pin
    
84. 
    
85.           /* Enable the UART3_RXD function on PTC16 */
    
86.           PORTE_PCR25 = PORT_PCR_MUX(0x3); // UART is alt3 function for this pin
    
87.       }
    
88.       if (TERM_PORT == UART5_BASE_PTR)
    
89.       {
    
90.                  /* Enable the UART3_TXD function on PTC17 */
    
91.           PORTE_PCR8 = PORT_PCR_MUX(0x3); // UART is alt3 function for this pin
    
92. 
    
93.           /* Enable the UART3_RXD function on PTC16 */
    
94.           PORTE_PCR9 = PORT_PCR_MUX(0x3); // UART is alt3 function for this pin
    
95.       }
    
96.       /* UART0 and UART1 are clocked from the core clock, but all other UARTs are
    
97.          * clocked from the peripheral clock. So we have to determine which clock
    
98.          * to send to the uart_init function.
    
99.          */
    
100.         if ((TERM_PORT == UART0_BASE_PTR) | (TERM_PORT == UART1_BASE_PTR))
     
101.             uart_init (TERM_PORT, core_clk_khz, TERMINAL_BAUD);
     
102.         else
     
103.        uart_init (TERM_PORT, periph_clk_khz, TERMINAL_BAUD);
     
104. }
     
105. /********************************************************************/
     
106. void trace_clk_init(void)
     
107. {
     
108.     /* Set the trace clock to the core clock frequency */
     
109.     SIM_SOPT2 |= SIM_SOPT2_TRACECLKSEL_MASK;
     
110. 
     
111.     /* Enable the TRACE_CLKOUT pin function on PTA6 (alt7 function) */
     
112.     PORTA_PCR6 = ( PORT_PCR_MUX(0x7));
     
113. }
     
114. /********************************************************************/
     
115. void fb_clk_init(void)
     
116. {
     
117.     /* Enable the clock to the FlexBus module */
     
118.         SIM_SCGC7 |= SIM_SCGC7_FLEXBUS_MASK;
     
119. 
     
120.      /* Enable the FB_CLKOUT function on PTC3 (alt5 function) */
     
121.     PORTC_PCR3 = ( PORT_PCR_MUX(0x5));
     
122. }
     
123. /********************************************************************/

首先寫(xiě)SIM_SCGC5寄存器。SCGC5表示的是System Clock Gating Control Register 5（系統(tǒng)時(shí)鐘門(mén)控制寄存器5）.系統(tǒng)集成模塊 --System integration module (SIM)--控制寄存器組中共有8個(gè)SCGC寄存器，它們分別控制不同外設(shè)所需要的時(shí)鐘的開(kāi)關(guān)，SCGC5寄存器控制的是PORTA~PORTE、TSI、REGFILE和LPTIMER時(shí)鐘的開(kāi)關(guān)，向?qū)��?yīng)的位寫(xiě)入1表示使能時(shí)鐘。第一段代碼分別打開(kāi)了PORTA~PORTE的時(shí)鐘開(kāi)關(guān)。

上面pll_init（unsigned char,unsigned char）函數(shù)用來(lái)增加系統(tǒng)時(shí)鐘。

1. unsigned char pll_init(unsigned char clk_option, unsigned char crystal_val)
   
2. {
   
3.   unsigned char pll_freq;
   
4. 
   
5.   if (clk_option > 3) {return 0;} //return 0 if one of the available options is not selected
   
6.   if (crystal_val > 15) {return 1;} // return 1 if one of the available crystal options is not available
   
7. //This assumes that the MCG is in default FEI mode out of reset.
   
8. 
   
9. // First move to FBE mode
   
10. #if (defined(K60_CLK) || defined(ASB817))
    
11.      MCG_C2 = 0;
    
12. #else
    
13. // Enable external oscillator, RANGE=2, HGO=1, EREFS=1, LP=0, IRCS=0
    
14.     MCG_C2 = MCG_C2_RANGE(2) | MCG_C2_HGO_MASK | MCG_C2_EREFS_MASK;
    
15. #endif
    
16. 
    
17. // after initialization of oscillator release latched state of oscillator and GPIO
    
18.     SIM_SCGC4 |= SIM_SCGC4_LLWU_MASK;
    
19.     LLWU_CS |= LLWU_CS_ACKISO_MASK;
    
20.   
    
21. // Select external oscilator and Reference Divider and clear IREFS to start ext osc
    
22. // CLKS=2, FRDIV=3, IREFS=0, IRCLKEN=0, IREFSTEN=0
    
23.   MCG_C1 = MCG_C1_CLKS(2) | MCG_C1_FRDIV(3);
    
24. 
    
25.   /* if we aren't using an osc input we don't need to wait for the osc to init */
    
26. #if (!defined(K60_CLK) && !defined(ASB817))
    
27.     while (!(MCG_S & MCG_S_OSCINIT_MASK)){}; // wait for oscillator to initialize
    
28. #endif
    
29. 
    
30.   while (MCG_S & MCG_S_IREFST_MASK){}; // wait for Reference clock Status bit to clear
    
31. 
    
32.   while (((MCG_S & MCG_S_CLKST_MASK) >> MCG_S_CLKST_SHIFT) != 0x2){}; // Wait for clock status bits to show clock source is ext ref clk
    
33. 
    
34. // Now in FBE
    
35. 
    
36. #if (defined(K60_CLK))
    
37.    MCG_C5 = MCG_C5_PRDIV(0x18);
    
38. #else
    
39. // Configure PLL Ref Divider, PLLCLKEN=0, PLLSTEN=0, PRDIV=5
    
40. // The crystal frequency is used to select the PRDIV value. Only even frequency crystals are supported
    
41. // that will produce a 2MHz reference clock to the PLL.
    
42.   MCG_C5 = MCG_C5_PRDIV(crystal_val); // Set PLL ref divider to match the crystal used
    
43. #endif
    
44. 
    
45.   // Ensure MCG_C6 is at the reset default of 0. LOLIE disabled, PLL disabled, clk monitor disabled, PLL VCO divider is clear
    
46.   MCG_C6 = 0x0;
    
47. // Select the PLL VCO divider and system clock dividers depending on clocking option
    
48.   switch (clk_option) {
    
49.     case 0:
    
50.       // Set system options dividers
    
51.       //MCG=PLL, core = MCG, bus = MCG, FlexBus = MCG, Flash clock= MCG/2
    
52.       set_sys_dividers(0,0,0,1);
    
53.       // Set the VCO divider and enable the PLL for 50MHz, LOLIE=0, PLLS=1, CME=0, VDIV=1
    
54.       MCG_C6 = MCG_C6_PLLS_MASK | MCG_C6_VDIV(1); //VDIV = 1 (x25)
    
55.       pll_freq = 50;
    
56.       break;
    
57.    case 1:
    
58.       // Set system options dividers
    
59.       //MCG=PLL, core = MCG, bus = MCG/2, FlexBus = MCG/2, Flash clock= MCG/4
    
60.      set_sys_dividers(0,1,1,3);
    
61.       // Set the VCO divider and enable the PLL for 100MHz, LOLIE=0, PLLS=1, CME=0, VDIV=26
    
62.       MCG_C6 = MCG_C6_PLLS_MASK | MCG_C6_VDIV(26); //VDIV = 26 (x50)
    
63.       pll_freq = 100;
    
64.       break;
    
65.     case 2:
    
66.       // Set system options dividers
    
67.       //MCG=PLL, core = MCG, bus = MCG/2, FlexBus = MCG/2, Flash clock= MCG/4
    
68.       set_sys_dividers(0,1,1,3);
    
69.       // Set the VCO divider and enable the PLL for 96MHz, LOLIE=0, PLLS=1, CME=0, VDIV=24
    
70.       MCG_C6 = MCG_C6_PLLS_MASK | MCG_C6_VDIV(24); //VDIV = 24 (x48)
    
71.       pll_freq = 96;
    
72.       break;
    
73.    case 3:
    
74.       // Set system options dividers
    
75.       //MCG=PLL, core = MCG, bus = MCG, FlexBus = MCG, Flash clock= MCG/2
    
76.       set_sys_dividers(0,0,0,1);
    
77.       // Set the VCO divider and enable the PLL for 48MHz, LOLIE=0, PLLS=1, CME=0, VDIV=0
    
78.       MCG_C6 = MCG_C6_PLLS_MASK; //VDIV = 0 (x24)
    
79.       pll_freq = 48;
    
80.       break;
    
81.   }
    
82.   while (!(MCG_S & MCG_S_PLLST_MASK)){}; // wait for PLL status bit to set
    
83. 
    
84.   while (!(MCG_S & MCG_S_LOCK_MASK)){}; // Wait for LOCK bit to set
    
85. 
    
86. // Now running PBE Mode
    
87. 
    
88. // Transition into PEE by setting CLKS to 0
    
89. // CLKS=0, FRDIV=3, IREFS=0, IRCLKEN=0, IREFSTEN=0
    
90.   MCG_C1 &= ~MCG_C1_CLKS_MASK;
    
91. 
    
92. // Wait for clock status bits to update
    
93.   while (((MCG_S & MCG_S_CLKST_MASK) >> MCG_S_CLKST_SHIFT) != 0x3){};
    
94. 
    
95. // Now running PEE Mode
    
96. 
    
97. return pll_freq;
    
98. } //pll_init

    這個(gè)函數(shù)中兩個(gè)參數(shù)clk_option和crystal_val是兩個(gè)枚舉變量（enum），從它們的定義來(lái)看它們的取值范圍是0~3和0~15.所以函數(shù)開(kāi)始先進(jìn)行有效性判斷。

        MCG表示的是 Multipurpose Clock Generator（多用途時(shí)鐘發(fā)生器）.MCG模塊向MCU提供幾個(gè)時(shí)鐘源選擇。這個(gè)模塊包含了一個(gè) frequency-locked loop (FLL)和一個(gè) phase-locked loop (PLL).FLL可以通過(guò)內(nèi)部的或外部的參考時(shí)鐘源來(lái)控制，PLL可以通過(guò)外部參考時(shí)鐘來(lái)控制。模塊可以選擇FLL或PLL的輸出時(shí)鐘或者內(nèi)部或外部時(shí)鐘源作為MCU的系統(tǒng)時(shí)鐘。上面MCG_2指的是 MCG Control 2 Register. MCG一共有9種操作模式：FEI, FEE, FBI, FBE, PBE, PEE, BLPI,BLPE,and Stop. 不同運(yùn)行模式的功耗互不相同，要進(jìn)入各個(gè)模式需要寫(xiě)MCG_1~MCG_6寄存器組中某幾個(gè)寄存器中的某幾個(gè)位。  我們可以這樣說(shuō)，采用內(nèi)部組件的模式所消耗的功率少于采用外部組件的模式。而MCG包括兩種專(zhuān)門(mén)為低功率應(yīng)用設(shè)計(jì)的模式——旁通低功耗內(nèi)部（BLPI）和旁通低功耗外部（BLPE）。驅(qū)動(dòng)BLPI模式的總線頻率要比BLPE 模式低，因此BLPI 模式消耗的功率最小。下圖2總結(jié)了每一種運(yùn)行模式的功耗。

    在sysinit()函數(shù)中對(duì)pll_init(unsigned char,unsigned char)函數(shù)的引用包含兩個(gè)參數(shù)：CORE_CLK_MHZ和REF_CLK，從其定義可以看出其值分別為PLL96和XTAL8，分別代表2和3.K60_CLK 被定義為1.因此，在引用pll_init(unsigned char,unsigned char)函數(shù)時(shí)根據(jù)條件編譯，執(zhí)行的語(yǔ)句依次是： 

1. // First move to FBE mode
   
2. MCG_C2 = 0;
   
3. 
   
4. // after initialization of oscillator release latched state of oscillator and GPIO
   
5.     SIM_SCGC4 |= SIM_SCGC4_LLWU_MASK;
   
6.     LLWU_CS |= LLWU_CS_ACKISO_MASK;
   
7. 
   
8. // Select external oscilator and Reference Divider and clear IREFS to start ext osc
   
9. // CLKS=2, FRDIV=3, IREFS=0, IRCLKEN=0, IREFSTEN=0
   
10.   MCG_C1 = MCG_C1_CLKS(2) | MCG_C1_FRDIV(3);
    
11. 
    
12. // wait for Reference clock Status bit to clear
    
13. while (MCG_S & MCG_S_IREFST_MASK){};
    
14. 
    
15. // Wait for clock status bits to show clock source is ext ref clk
    
16. while (((MCG_S & MCG_S_CLKST_MASK) >> MCG_S_CLKST_SHIFT) != 0x2){};
    
17. 
    
18. MCG_C5 = MCG_C5_PRDIV(0x18);
    
19. 
    
20. /* Ensure MCG_C6 is at the reset default of 0. LOLIE disabled, PLL disabled, clk monitor disabled, PLL VCO divider is clear*/
    
21.   MCG_C6 = 0x0;
    
22. 
    
23. // Set system options dividers
    
24. //MCG=PLL, core = MCG, bus = MCG/2, FlexBus = MCG/2, Flash clock= MCG/4
    
25.    set_sys_dividers(0,1,1,3);
    
26. // Set the VCO divider and enable the PLL for 96MHz, LOLIE=0, PLLS=1, CME=0, VDIV=24
    
27.       MCG_C6 = MCG_C6_PLLS_MASK | MCG_C6_VDIV(24); //VDIV = 24 (x48)
    
28.       pll_freq = 96;
    
29. 
    
30. while (!(MCG_S & MCG_S_PLLST_MASK)){}; // wait for PLL status bit to set
    
31. 
    
32.   while (!(MCG_S & MCG_S_LOCK_MASK)){}; // Wait for LOCK bit to set
    
33. 
    
34. // Now running PBE Mode
    
35. 
    
36. // Transition into PEE by setting CLKS to 0
    
37. // CLKS=0, FRDIV=3, IREFS=0, IRCLKEN=0, IREFSTEN=0
    
38.   MCG_C1 &= ~MCG_C1_CLKS_MASK;
    
39. 
    
40. // Wait for clock status bits to update
    
41.   while (((MCG_S & MCG_S_CLKST_MASK) >> MCG_S_CLKST_SHIFT) != 0x3){};
    
42. 
    
43. // Now running PEE Mode
    
44. 
    
45. return pll_freq;

    最后，系統(tǒng)運(yùn)行在PEE模式下。